I have never seen a picture from a minimig with a 2.04 bootscreen.
But the minimigtg68 can boot all versions of kickstartrom.

Now I found a little but important difference in the 68sec000 and the
TG68 IP Core.

The tg68 is a 68000 Clone. But the 68sec000 insn't a 68000 and isn't
a 68010. That is the Problem.

The Move from SR is priviligated in the 68sec000. Kick >= 2.04 use
this Instruction to check the CPU Type.
For the kick 2.04 is the 68sec000 a 68010. But the 68sec000 has the
exception stack frames from the 68000. That can't work without a
patch.

But the TG68 use the Move from sr in user state and use also the
68000 exception stack frames. That works fine.

I think the TG68 IP Core is the better choose for the minimig!

Viele Grüße
TobiFlex - the creator of the TG68 Core ;-)

android@... wrote:

> Should be easy to syntetise the source for the DE2 board in a
> DE270?

The only issue I think you'll have is the SDRAM controller, as the
configuration of the SDRAM on the DE2-70 differs from the DE2.

I have ported the DE2 to custom hardware with differing SDRAM and it boots
Kickstart and runs the floppy disk emulation menu - although I can't get it
to successfully boot a floppy image. Having said that, I have the same
problem on a DE2 when I build the DE2 version myself as well, so I'm not
convinced there's not a problem elsewhere...

The SDRAM on my platform is larger than the DE2, but the SDRAM controller
appears to handle it because it drives 1 more address line than the SDRAM on
the DE2 requires. I punched it out to the top level and, as I said,
Kickstart boots so I'm reasonably confident that it's refreshing the SDRAM
on my platform correctly...

Every other aspect of the design should run as-is...

Regards,

--
|              Mark McDougall                | "Electrical Engineers do it
|  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"

Hi people

I'm new to this forum.

I'm a hardware engineer and i bought some Xilinx FPGA
evaluation boards, including and XUP-V2P, for hobby
purposses.
I never worked with Altera FPGA's, and i'm planing to buy a
board from Terasic.
I wish to buy a board to make work Minimig but i wish to buy
a powerfull one that can be expanded in a near future.
I saw on the Terasic web page the DE1, DE2 and DE2-70, for
the price difference of the DE2 and DE2-70, around 100%, i
think that the DE2-70 is more interesting because doubles
memory lenght.

Have tested any of you the Minimig on a DE2-70 board?
Should be easy to syntetise the source for the DE2 board in a
DE270?
I ask this because i doesn't have any experience with Altera
devices until now and i don't know if it will be difficult to port
the source to a DE2-70 pcb.

Best Regards

Xavier Ruiz

Hi co_ze,

--- In minimigtg68@yahoogroups.com, "co_ze" <akaraduman@...> wrote:
>
> Hello Everyone !
> I just got myself a DE1 kit to build myself Tobi's 68k softcore
> minimig. Before I try the minimig sources, I'ld like to play with it
> and get the feel of it though. So I'ld appreciate if you know any
> sites which is merciful to the newcomer. I took a look at the
> tutorials at the cd that came with the kit, but all I found was
> complicated stuff like building DSPs and softcore NIOS processor and
> stuff. I just want to make simple stuff like a binary adder, bind
the
> switches and leds to input and output and stuff like that.
>
> will be grateful for any tips.
>

Buried away in the Altera University Program is a page with DE1/DE2
specific lessons/tutorials etc. :
http://www.altera.com/education/univ/materials/manual/unv-lab-
manual.html

There are verilog or vhdl lessons which are near identical depending
on your preference.

All the up-to-date manuals regarding QuartusII are at:
http://www.altera.com/literature/lit-qts.jsp
Though that is a little easier to find :)

Hope this helps,
Leslie

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hereby notified that any dissemination, distribution or copying of this
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Hello Everyone !
I just got myself a DE1 kit to build myself Tobi's 68k softcore
minimig. Before I try the minimig sources, I'ld like to play with it
and get the feel of it though. So I'ld appreciate if you know any
sites which is merciful to the newcomer. I took a look at the
tutorials at the cd that came with the kit, but all I found was
complicated stuff like building DSPs and softcore NIOS processor and
stuff. I just want to make simple stuff like a binary adder, bind the
switches and leds to input and output and stuff like that.

will be grateful for any tips.

--- In minimigtg68@yahoogroups.com, "Leslie" <layling@...> wrote:
>
> Hi Mark,
>
> --- In minimigtg68@yahoogroups.com, Mark McDougall <msmcdoug@> wrote:
>
> > Are you using the opencores IDE controller? Or rolling your own in
> some sort
> > of hardware/software state machine?
>
> Nothing so elaborate.
> Just mimicking the behaviour of the GAYLE chip in the Amiga600 (A1200
> has identical functionality aswell).
>
> Gayle is (basically) an updated version of the Gary chip in the A500.
> Provides an IDE + PCMCIA interface on top of the Gary functions.
>
Hi Leslie!

Please check out this web page:
http://www.students.tut.fi/~leinone3/ide/

this file could give you some hints:
http://www.students.tut.fi/~leinone3/ide/a600ide_preliminary.abl


Best Regards
Jaime

--- In minimigtg68@yahoogroups.com, "Leslie" <layling@...> wrote:

> It's getting upset by the '&' ampersand in the project name.
> Illegal chars file names (as far as Quartus is concerned) are:
> ^&?*|<>;'
> If you have one of those characters, you should get a message like:
> http://au.geocities.com/redskulldc/q_ill.gif
>
> Xilinx's ISE/EDK tools on the other hand don't like spaces anywhere
> in the path name of any files in a project, at least that's my
> experience.
>
> Hope this helps,
> Leslie

Yes, thanks to all! I can now compile. Time to start playing!

Hi,

--- In minimigtg68@yahoogroups.com, "mrmartian1271" <daryl@...> wrote:
> >
> > I'm using Quartus 7.2sp1, and can't load the project. I get an
error
> > about invalid characters in the name. What version are you using?
> >
>
> Okay - bad question (what version?), since I see others have used
this
> version. But, that also tells me that this should load just fine!
Argh!
>

It's getting upset by the '&' ampersand in the project name.
Illegal chars file names (as far as Quartus is concerned) are:
^&?*|<>;'
If you have one of those characters, you should get a message like:
http://au.geocities.com/redskulldc/q_ill.gif

Xilinx's ISE/EDK tools on the other hand don't like spaces anywhere
in the path name of any files in a project, at least that's my
experience.

Hope this helps,
Leslie

--- In minimigtg68@yahoogroups.com, "mrmartian1271" <daryl@...> wrote:
>
> --- In minimigtg68@yahoogroups.com, "mrmartian1271" <daryl@> wrote:
> >
> > I'm using Quartus 7.2sp1, and can't load the project. I get an error
> > about invalid characters in the name. What version are you using?
> >
>
> Okay - bad question (what version?), since I see others have used this
> version. But, that also tells me that this should load just fine! Argh!
>
I think i got the same error.
I had to move the project directory to the root of my drive.
I think quartus doesn't like spaces in path or too long paths.

Per Olav

--- In minimigtg68@yahoogroups.com, "mrmartian1271" <daryl@...> wrote:
>
> I'm using Quartus 7.2sp1, and can't load the project. I get an error
> about invalid characters in the name. What version are you using?
>

Okay - bad question (what version?), since I see others have used this
version. But, that also tells me that this should load just fine! Argh!

I'm using Quartus 7.2sp1, and can't load the project. I get an error
about invalid characters in the name. What version are you using?

Hi Leslie,
I have add a photo of my CF-DE1 Connector. I hasn't found the Time
for the IDE hack yet. But I hope it is not to difficult.

Viele Grüße
TobiFlex



--- In minimigtg68@yahoogroups.com, "Leslie" <layling@...> wrote:
>
> Hi Tobiflex,
>
>
> --- In minimigtg68@yahoogroups.com, "TobiFlex" <t.gubener@> wrote:
> >
> > Hi,
> > I would like to add an autoconfig 4MB Fastram and an IDE port
like
> the
> > internal A1200 Port to the MinimigTG68 Core.
> > My first try of autoconfigure code for the fast ram don't work.
> > For the IDE Port I found some Informations with address $DA0000
and
> > $DE0000 and $F20000. What is rigth???
> > Where can I found the needed Informations???
> > Please help me!
> >
> > Viele Grüße
> > TobiFlex
> >
>
> How far have you got with the IDE interface?
>
> Only just seen your posts since I have been away with work.
>
> I started with the hardware which will be required first:
> I've already built the hardware interface to use a CF adapter on
one
> of the DE1/DE2's GPIO ports, have just uploaded a photo:
>
http://gamesource.groups.yahoo.com/group/minimigtg68/spnew/view/62fc?
> i=32
> It's mainly straight through connections, except for rerouting the
> 3.3v, and a few other conflicts between the IDE 40pins and the
GPIO
> 40pins.
> Can post schematic on weekend if anyone is interested.
>
> Have started on the software, but not complete yet.
> Software seems pretty simple:
> 1. State machine in Gayle(GARY) which is checked by kickstart at
> reset time to indicate prescence of IDE interface.
> 2. another INTREQ and INTENA type registers on gayle used by the
IDE.
> 3. IDE uses INT2 on real amiga, just need to add an extra
interrupt
> line into the interrupt controller code, at same priority.
>
> Happy to share what info I have unless you have figured it out
> already?
>
> Cheers,
> Leslie
>

Hi Mark,

--- In minimigtg68@yahoogroups.com, Mark McDougall <msmcdoug@...> wrote:

> Are you using the opencores IDE controller? Or rolling your own in
some sort
> of hardware/software state machine?

Nothing so elaborate.
Just mimicking the behaviour of the GAYLE chip in the Amiga600 (A1200
has identical functionality aswell).

Gayle is (basically) an updated version of the Gary chip in the A500.
Provides an IDE + PCMCIA interface on top of the Gary functions.

It provides a (slow) PIO mode IDE interface.
No 68K programming required, since it is all in the kickstart:
scsi.device

Service manual for the A600 + schematics can be found at:
http://www.shiftreload.com.au/users/4x4/schematics/a600.zip
5-12B.png is the sheet which shows the A600's IDE connector.

Off to bed, just driven 850Km's today ZZZzzzz....
Talk later about the 2000 case etc.

Cheers,
Leslie

Leslie wrote:

> Have started on the software, but not complete yet.
> Software seems pretty simple:
> 1. State machine in Gayle(GARY) which is checked by kickstart at
> reset time to indicate prescence of IDE interface.
> 2. another INTREQ and INTENA type registers on gayle used by the IDE.
> 3. IDE uses INT2 on real amiga, just need to add an extra interrupt
> line into the interrupt controller code, at same priority.
>
> Happy to share what info I have unless you have figured it out
> already?

Are you using the opencores IDE controller? Or rolling your own in some sort
of hardware/software state machine?

Regards,

--
|              Mark McDougall                | "Electrical Engineers do it
|  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"

Hi Tobiflex,


--- In minimigtg68@yahoogroups.com, "TobiFlex" <t.gubener@...> wrote:
>
> Hi,
> I would like to add an autoconfig 4MB Fastram and an IDE port like
the
> internal A1200 Port to the MinimigTG68 Core.
> My first try of autoconfigure code for the fast ram don't work.
> For the IDE Port I found some Informations with address $DA0000 and
> $DE0000 and $F20000. What is rigth???
> Where can I found the needed Informations???
> Please help me!
>
> Viele Grüße
> TobiFlex
>

How far have you got with the IDE interface?

Only just seen your posts since I have been away with work.

I started with the hardware which will be required first:
I've already built the hardware interface to use a CF adapter on one
of the DE1/DE2's GPIO ports, have just uploaded a photo:
http://gamesource.groups.yahoo.com/group/minimigtg68/spnew/view/62fc?
i=32
It's mainly straight through connections, except for rerouting the
3.3v, and a few other conflicts between the IDE 40pins and the GPIO
40pins.
Can post schematic on weekend if anyone is interested.

Have started on the software, but not complete yet.
Software seems pretty simple:
1. State machine in Gayle(GARY) which is checked by kickstart at
reset time to indicate prescence of IDE interface.
2. another INTREQ and INTENA type registers on gayle used by the IDE.
3. IDE uses INT2 on real amiga, just need to add an extra interrupt
line into the interrupt controller code, at same priority.

Happy to share what info I have unless you have figured it out
already?

Cheers,
Leslie

Thank you Frederic!

Your Informations are very importend for my next steps.

Viele Grüße
TobiFlex

--- In minimigtg68@yahoogroups.com, "requin_frederic2"
<requin_frederic2@...> wrote:
>
> Follow-up:
>
> the EAB thread says that GayleID is 0xD0.
>
> Good luck !
>

Follow-up:

the EAB thread says that GayleID is 0xD0.

Good luck !

--- In minimigtg68@yahoogroups.com, "TobiFlex" <t.gubener@...> wrote:
>
> Hi,
> I would like to add an autoconfig 4MB Fastram and an IDE port like
the
> internal A1200 Port to the MinimigTG68 Core.
> My first try of autoconfigure code for the fast ram don't work.
> For the IDE Port I found some Informations with address $DA0000 and
> $DE0000 and $F20000. What is rigth???
> Where can I found the needed Informations???
> Please help me!
>
> Viele Grüße
> TobiFlex
>

Hello Tobias,

you can find some useful information in Linux or BSD sources for
amiga (search for amigayle.h)

There is also this thread on EAB :
http://eab.abime.net/archive/index.php/t-23924.html
The question is from bluea (aka Thomas from NatAmi project) :-).

From what I remember, $DA0000 and $DE0000 are the Gayle addresses.
The A4000 has a different address for the IDE port, it is $DD2000.

To have the IDE port correctly detected, the Exec function ReadGayle
(offset -816) must find the Gayle ID at address $DE1000. Apparently,
the Gayle ID is sent through a shift register, bit 7 is the serial
out. The shift register is re-initlaized when you write to $DE1000,
one bit is shifted when you read from $DE1000. I do not know the
Gayle ID value, you have to try on a real A1200.

If no Gayle chip is present, you find a mirror of the Chip registers,
hence the INTENA register trick to detect Gayle.

Here is the ReadGayle from Exec:

Exec_ReadGayle
     moveq   #$0,D0
     movea.l A5,A0
     lea     ReadGayle_Sup(PC),A5
     jmp     _LVOSupervisor(A6)
ReadGayle_Sup
     movea.l A0,A5
     lea     _custom,A0
     lea     $DE1000.l,A1
     ori.w   #$700,SR
     move.w  $1C(A0),-(A7)
     move.w  #$BFFF,$9A(A1)
     move.w  #$3FFF,D1
     cmp.w   $1C(A0),D1
     bne.b   .GayleFound
     move.w  D1,$9A(A1)
     tst.w   $1C(A0)
     bne.b   .GayleFound
     moveq   #$0,D1
.GayleFound
     move.w  #$3FFF,$9A(A0)
     ori.w   #$8000,(A7)
     move.w  (A7)+,$9A(A0)
     tst.w   D1
     beq.b   .NoGayle
     move.b  D0,(A1)
     bsr.b   .ReadOneBit
     bsr.b   .ReadOneBit
     bsr.b   .ReadOneBit
     bsr.b   .ReadOneBit
     bsr.b   .ReadOneBit
     bsr.b   .ReadOneBit
     bsr.b   .ReadOneBit
     bsr.b   .ReadOneBit
.NoGayle
     cmp.b   #$FF,D0
     bne.b   .End
     moveq   #$0,D0
.End
     rte
.ReadOneBit
     move.b  (A1),D1
     lsl.b   #1,D1
     addx.b  D0,D0
     rts

I hope this helps.

Regards,

Frederic

Hi,
I would like to add an autoconfig 4MB Fastram and an IDE port like the
internal A1200 Port to the MinimigTG68 Core.
My first try of autoconfigure code for the fast ram don't work.
For the IDE Port I found some Informations with address $DA0000 and
$DE0000 and $F20000. What is rigth???
Where can I found the needed Informations???
Please help me!

Viele Grüße
TobiFlex

--- In minimigtg68@yahoogroups.com, "mathesar77" <mathesar77@...>
wrote:

> Hi Frederic,
>
> That sounds very good! I think it is a good idea to change the DMA
> sequencers. The fact that every module has its own sequencer and
> address generator is one of the reasons Agnus is such a large
> module. All the address generators and the multiplexer that
combines
> all the address busses could be replaced by one generic address
> generator that is used by all modules, including the blitter and
> copper.
>
> The magic mystical logic is indeed a strange thing :-) and it
> doesn't work that well either; for example, on my minimig,
> the "insert disk" screen of Pinball fantasies doesn't look right
and
> I think the magic mystical code is part of the problem.
>
> Mathesar77
>

Hello Dennis,

I have finished the address decoder. I have 70+ write strobe signals
out of it and a big mux for the register read. I took advantage of
some register grouping like the bitplane pointers, sprites registers
or audio registers to reduce the number of signals. The decoder
supports 16-bit or 32-bit bus trough a VHDL parameter.

Since the DMA sequencer is mostly composed of two small RAMs, it is
actually fully reconfigurable through some extra registers.
The DMA sequence can be adapted to your need. Of course, you can mess
it up bug time if you are not careful :-).

The AAA chipset looks promising.

Regards,

Frederic

--- In minimigtg68@yahoogroups.com, "vectrex0" <vectrex@...> wrote:
>
> plz tobi make a scrollable minimig menu ;)
>

As far as I know (haven't tried Tobiflex' core yet), the DE1/DE2
version uses the same basic firmware as the Minimig rev1.1. That means
that you can scroll through the Minimig floppy select menu just fine.

Mathesar77

--- In minimigtg68@yahoogroups.com, "requin_frederic2"
<requin_frederic2@...> wrote:
>
> Hello Dennis,
>
> I am currently rewriting minimig with AGA/AAA features.
> So far, I have done the video beam controller with all the ECS/AGA
> registers. IMHO, your PAL timings look perfect. It took me few
days to
> have the NTSC timings OK.
> I did not really implemented long lines / short lines. Since my
hbeam
> runs at 28 MHz, I just stop the line @ half a color clock.
> My guess is that on a real Amiga, there is a half color cycle
delay
> inserted in Denise when outputting a long line (hence the 4.5 or
8.5
> cycles rule between DDFSTRT and DIWSTRT).
> Now, I am working on the DMA sequencer. I took a different
approach : I
> have two microsequencers. One for bitplane DMAs (sequencer #1) and
one
> for "other" DMAs (sequencer #0).
> Sequencer #1 's output replaces sequencer #0 's output when hbeam
is
> within the DDFSTRT - DDFSTOP range (ddfenable = 1).
> BTW, the ddfenable flag is generated slightly differently: it is a
flip-
> flop that is set by DDFSTRT comparator and clear by DDFSTOP
comparator
> (this one is delayed by the fetch length 2,4 or 8 cycles,
depending of
> FMODE and resolution). I do not have to use the "magic mystical
logic"
> of Agnus.v :-).
>
> Regards,
>
> Frederic
>
Hi Frederic,

That sounds very good! I think it is a good idea to change the DMA
sequencers. The fact that every module has its own sequencer and
address generator is one of the reasons Agnus is such a large
module. All the address generators and the multiplexer that combines
all the address busses could be replaced by one generic address
generator that is used by all modules, including the blitter and
copper.

The magic mystical logic is indeed a strange thing :-) and it
doesn't work that well either; for example, on my minimig,
the "insert disk" screen of Pinball fantasies doesn't look right and
I think the magic mystical code is part of the problem.

Mathesar77

--- In minimigtg68@yahoogroups.com, "mathesar77" <mathesar77@...> wrote:
>
> Nice to see all the active development going on here!
>
> If you have any questions regarding Minimig, feel free to ask.
>
> Mathesar77 (aka Dennis @ Amiga.org)
>

Hi Dennis,

Nice to know you are around here!
I've also been tinkering with modifying the code for ECS compatibility,
though I suspect Frederic is considerably further advanced with his
work than I am :)

Been a considerable time since I played with a "real" 500, but it's
coming back to me slowly....

All the best, and a Happy new year to everyone,
Leslie

--- In minimigtg68@yahoogroups.com, "mathesar77" <mathesar77@...> wrote:
>
> Nice to see all the active development going on here!
>
> If you have any questions regarding Minimig, feel free to ask.
>
> Mathesar77 (aka Dennis @ Amiga.org)
>

Hello Dennis,

I am currently rewriting minimig with AGA/AAA features.
So far, I have done the video beam controller with all the ECS/AGA
registers. IMHO, your PAL timings look perfect. It took me few days to
have the NTSC timings OK.
I did not really implemented long lines / short lines. Since my hbeam
runs at 28 MHz, I just stop the line @ half a color clock.
My guess is that on a real Amiga, there is a half color cycle delay
inserted in Denise when outputting a long line (hence the 4.5 or 8.5
cycles rule between DDFSTRT and DIWSTRT).
Now, I am working on the DMA sequencer. I took a different approach : I
have two microsequencers. One for bitplane DMAs (sequencer #1) and one
for "other" DMAs (sequencer #0).
Sequencer #1 's output replaces sequencer #0 's output when hbeam is
within the DDFSTRT - DDFSTOP range (ddfenable = 1).
BTW, the ddfenable flag is generated slightly differently: it is a flip-
flop that is set by DDFSTRT comparator and clear by DDFSTOP comparator
(this one is delayed by the fetch length 2,4 or 8 cycles, depending of
FMODE and resolution). I do not have to use the "magic mystical logic"
of Agnus.v :-).

Regards,

Frederic

Nice to see all the active development going on here!

If you have any questions regarding Minimig, feel free to ask.

Mathesar77 (aka Dennis @ Amiga.org)

Laptev wrote:

> Where is formatted your SD-card ? I format SD-Card in
> windows_XP, selected FAT. I`m too can`t boot any disk or on other SD-card
> appears red screen,yellow scr,not detect sd-card. I format SD-card in
> digital fotocamera - all problem is absent.

  From memory, I don't think I have ever formatted this SD card. I bought it
- a micro SD in an SD adapter - to use on another FPGA project but it turned
out I needed a mini-SD! So it sat unused for a few months until Minimig was
released. Works OK on the initial release of Minimig-DE2...

I don't have a camera with SD but I should try the program Leslie
recommends... unfortunately I don't have a (working) SD card reader at home
atm... (cheap crap I bought just hangs windows XP when I put a card in it) :(

Regards,

--
|              Mark McDougall                | "Electrical Engineers do it
|  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"

Hi All,

Re:

>   File        : /Blitter.v
>   Uploaded by : redskulldc <layling@...>
>   Description : Initial mods to the blitter module to allow "big-
blits"


Just starting to add support for ECS.

Have added :
05C  BLTSIZV - Blitter V size (for 15 bit vertical start)
05E  BLTSIZH - Blitter H size and start (for 11 bit H size)
up to a max size of 32768x32768

They happily co-exist with the old BLTSIZE register.

050  BLTxPTH - Blitter pointer to x (high 5 bits)(3 in OCS)
etc.
Dennis' code already had support for the 5 bits in the high
registers, so no changes were required.

* Minimig bombs first time you boot, I assume because KS/WB can't
identify the feature set correctly. Still reports as OCS Agnus/Denise
*
After a RESET from the pop-up menu it works fine ever after.


Will keep working on it, still a long way to go of course. :)

Cheers,
Leslie

Hello,

This email message is a notification to let you know that
a file has been uploaded to the Files area of the minimigtg68
group.

   File        : /Blitter.v
   Uploaded by : redskulldc <layling@...>
   Description : Initial mods to the blitter module to allow "big-blits"

You can access this file at the URL:
http://groups.yahoo.com/group/minimigtg68/files/Blitter.v

To learn more about file sharing for your group, please visit:
http://help.yahoo.com/l/us/yahoo/groups/original/members/web/index.htmlfiles

Regards,

redskulldc <layling@...>