--- In minimigtg68@yahoogroups.com, Mark McDougall <msmcdoug@...> wrote:
>
> requin_frederic2 wrote:
>
> > I am wondering if I should keep the two clocks or if
> > I can clock enable the TG68 with the 86 MHz. What do you think ?
>
> I'm pretty sure that clocks from the same PLL that are multiples of one
> another are guaranteed to be phase-aligned!?! So you could run a slower
> clock and treat them as synchronous I believe. I haven't tried this though.
>

I actually do that on some of my designs !
With the PLL along with the clocks, I generate a clock that is a short pulse
centered on the instant where all the rising edges are together.

Then I use this short pulse to reset a shift register that tells me on what
clock period I am in.

example:

bus_clk : 21.5 MHz
ram_clk : 86 MHz (4 x bus_clk)
seq_rst : 1/6 of bus_clk (~3.5 MHz), 350 deg phase, 6% duty cycle.

HTML output from Quartus II Megawizard is very useful for tuning the pulse.


In VHDL :
SIGNAL rclk_cyc : STD_LOGIC_VECT(3 DOWNTO 0);

PROCESS(reset_n, ram_clk, seq_rst)
BEGIN
IF (reset_n = '0') THEN
rclk_cyc <= "0000";
ELSIF (rising_edge(ram_clk)) THEN
IF (seq_rst = '1') THEN
rclk_cyc <= "0001";
ELSE
rclk_cyc <= rclk_cyc(2 DOWNTO 0) & rclk_cyc(3);
END IF;
END IF;
END PROCESS;

You can safely read registered signals from clock domain "bus_clk" in clock
domain "ram_clk" when : rclk_cyc(0/1/2) = '1'. For rclk_cyc(3) = '1', you can't.
You have to delay the signal first.

I really prefer this method than the gated clock method I find so often in open
source designs.

Regards,

Frederic