Hello Mark,

How is it going down under ?

I plan to use it on the boot menu of the MCC board (see:
www.arcaderetrogaming.com), on the Amiga core and as the sd-card/floppy
controller of the C64 core. It is a lot easier to manage FAT filesystem with a
68000 than with a 6510 :-).

Now, I am working on a unified cache implementation for TG68.
I think I can get a 8KB 4-way associative cache (21.5 MHz on the CPU side, 86
MHz on the SDRAM side). I am wondering if I should keep the two clocks or if I
can clock enable the TG68 with the 86 MHz.
What do you think ?

Frederic

--- In minimigtg68@yahoogroups.com, Mark McDougall <msmcdoug@...> wrote:
>
> requin_frederic2 wrote:
>
> > For those who wants to play with TG68:
> > * "state_out" signal : 00: fetch cycles, 01: decode cycles, 10: data read
cycles, 11: data write cycles.
> > * "decodeOPC" : seems to be equal to 1 only when state_out = 01.
> > * "reset", "UDS", "LDS" and "IPL" are low active.
> > * "wr" signal : 0=write, 1=read.
>
> I'm using TG68 for NeoGeo. The system clock is 25MHz, though the TG68 core
> is clock-enabled at 12.5MHz on a Cyclone II C6 (TerASIC DE1).
>
> I generate a 25MHz write pulse from the write signal, and need to stretch
> DTACK in general. It's (also) bridged to the opencores yadmc (wishbone).
>
> Fun stuff. What are you planning to use it for?
>
> Regards,
>
> --
> | Mark McDougall | "Electrical Engineers do it
> | <http://members.iinet.net.au/~msmcdoug> | with less resistance!"
>