requin_frederic2 wrote:

> For those who wants to play with TG68:
> * "state_out" signal : 00: fetch cycles, 01: decode cycles, 10: data read
cycles, 11: data write cycles.
> * "decodeOPC" : seems to be equal to 1 only when state_out = 01.
> * "reset", "UDS", "LDS" and "IPL" are low active.
> * "wr" signal : 0=write, 1=read.

I'm using TG68 for NeoGeo. The system clock is 25MHz, though the TG68 core
is clock-enabled at 12.5MHz on a Cyclone II C6 (TerASIC DE1).

I generate a 25MHz write pulse from the write signal, and need to stretch
DTACK in general. It's (also) bridged to the opencores yadmc (wishbone).

Fun stuff. What are you planning to use it for?

Regards,

--
| Mark McDougall | "Electrical Engineers do it
| <http://members.iinet.net.au/~msmcdoug> | with less resistance!"