Ok, I found the problem.
I slightly changed the AS# generation and the address decoder logic.
Now, everything runs fine.

On a cyclone III speed grade C8, I can clock the TG68 at 25 MHz.
I have decided to clock it at 21 MHz. Anyway, the core is very fast : wothout
the top level that stretches the memory access to 4 cycles, it only needs 2
cycles for a 1-word instruction and 3 cycles for a 2-word instruction. Overall
it is 9 times faster than a 7 MHz 68000.

For those who wants to play with TG68:
* "state_out" signal : 00: fetch cycles, 01: decode cycles, 10: data read
cycles, 11: data write cycles.
* "decodeOPC" : seems to be equal to 1 only when state_out = 01.
* "reset", "UDS", "LDS" and "IPL" are low active.
* "wr" signal : 0=write, 1=read.

If you want to use only tg68_fast, here is how I do it myself:

clk_ena <= '1' WHEN (clk_ena_in = '1') AND ((dtack_n = '0') OR (state_out =
"01") OR (decodeOPC = '1')) ELSE '0';
as_n <= UDS AND LDS;

I clock the memory accesses on the falling edges and TG68 on the rising edges.

Regards,

Frederic

--- In minimigtg68@yahoogroups.com, "requin_frederic2" <requin_frederic2@...>
wrote:
>
> Hello Tobias,
>
> I have a test program with a LEA $2000.W,A0, I had to replace it by LEA
$00002000.L,A0 to make it work on TG68.
>
> Any thoughts ?
>
> Regards
>
> Frederic
>