Hi and welcome here!
The V12e and V13 are old versions. Currently I'm working on a new Core Version
for the DE1, DE2 and C-One with the latest minimig source YQ090421. I'm also
change the SDRAM module to a 3-3-3 Timing. I hope this will solve the problems
with different SDRAM chips.
The C-One version will have HD support with a real IDE Connector.
The DE1 and DE2 version will don't have HD Support until the ARM Code with HD
image support is not available.

best
TobiFlex

> Hello there
>
> I'm new to this group (and FPGA in general) but this Minimig core is the best
thing has ever happened to the Altera DE1 board!
>
> I had to try a lot of versions before I found out that ONLY version 12e is
compatible with the newer Altera DE1 board using ZENTEL-labeled SDRAM chips.
Version 13 is incompatible with those new boards.
>
> So I wanted to ask:
>
> 1) What are the advantages/differences between V12e and V13? Is V12e supposed
to have disk write support?
>
> 2) If SDRAM is the problem, can you please compile V13 POF files with the V12e
SDRAM controller? Or can you provide basic instructions so I can do it myself?
>
> Thanks, Tobiflexx and the rest!
>