Hi Mark,
I'm glad that you work with the TG68 Core and that the bug was a
false alarm.

Regards,
TobiFlex
>
> Gary Hoyles wrote:
>
> > You seem to be crying wolf a lot, why not keep your errors to
yourself
> > untill you are !00% sure
>
> It may seem that way, but since I've been working on it pretty
much full
> time for the last 24 hours, I did actually get to the point where,
after a
> few solid hours staring at one particular problem, I thought I
_was_ sure...
> you can't ever be 100% sure either BTW.
>
> It wasn't immediately apparent to me that timing was an issue,
because
> although the system clock rate is reasonably high, the clock
enable is only
> 12MHz. Apparently that is still a problem. By lowering the clock
rate and
> keeping the 12MHz enable, it starts to behave more sanely.
>
> In any case, I stand by the assertion that the address is changing
while AS#
> is asserted, and that _will_ cause grief.
>
> FWIW I also note that there is a new version on opencores that is
not used
> in Minmig, despite the fact that AFAIK Minimig v13 was released
after
> changes were made to the core. I have no idea if the changes
address this issue.
>
> Regards,
>
> --
> | Mark McDougall | "Electrical
Engineers do it
> | <http://members.iinet.net.au/~msmcdoug> | with less
resistance!"
>