Hi Tobias,

OK, I've started a new thread because I think I know a little more about
what is going on. I still reserve the right to a big "DOH" if you point out
something stupid that I've done!! ;)

I should mention that I assert DTACKn immediately after AS# is asserted.

1) The core is changing address whilst AS# is asserted. From what I can
tell, this is a big no-no. It's a problem on writes as you can imagine. I
also appears to be holding AS# for quite a long time - longer than I would
think necessary. My temp fix was to strobe my RAM-write on the leading-edge
cycle of AS# asserted.

2) I *think* I've found an execution bug.

move.w #$1234, d0
move.l #$0810, a0

...works correctly. It writes $1234 to address $0810. However...

move.l #$0810, a0
move.w #$1234, d0

...doesn't work. It outputs #$1234 on *both* address and data_out buses!

I can provide you with signaltap traces if you like.

BTW TG68.vhd v1.01, TG68_fast.vhd v1.04 as from Minimig v13 disto.

Regards,

--
| Mark McDougall | "Electrical Engineers do it
| <http://members.iinet.net.au/~msmcdoug> | with less resistance!"