Mark McDougall wrote:

> Not sure what I don't understand here?!? I tried DTACK# tied low, then tried
> setting DTACK# to AS# in a clocked process. Am I asserting DTACK# too early
> here??? Otherwise, I don't really know how I'm supposed to use the TG68
> core... :(

OK, my fault for not understanding the 68k timing (haven't done a 68k design
myself).

I see that a standard 68000 bus cycle is 4 MPUCLKs long...

Is it true that to run the TG68 core at 12MHz I need a 24MHz clock_ena?

Regards,

--
| Mark McDougall | "Electrical Engineers do it
| <http://members.iinet.net.au/~msmcdoug> | with less resistance!"