Hi Tobias,

I'm attempting to instantiate your TG68 core in a project of mine and am
having trouble getting it to behave as I expect.

I've got a small internal RAM and have written a small test bootstrap ROM
for it. It reads the stack and reset vectors, jumps to the start and appears
to execute the code OK.

BUT...

(1) AS# and RW# are asserted during a memory write instruction, but not
de-asserted before the next instruction fetch starts. So the next
instruction is overwritten while being fetched... I did a quick fix by
pulsing the memory write on leading edge of AS# & RW#...

(2) The memory write drives the correct address and then asserts AS# and
RW#, but the write data doesn't appear on the data (out) bus until approx 10
cycles have elapsed!!! In that time it has fetched and executed a number of
BRA instructions!!!

Not sure what I don't understand here?!? I tried DTACK# tied low, then tried
setting DTACK# to AS# in a clocked process. Am I asserting DTACK# too early
here??? Otherwise, I don't really know how I'm supposed to use the TG68
core... :(

Regards,

--
| Mark McDougall | "Electrical Engineers do it
| <http://members.iinet.net.au/~msmcdoug> | with less resistance!"