Magnus Wedmark wrote:

> Thank you for the tip about the DDR-controller. I've seen it but I
> would really like a good example of it in use.. Have you seen some?
> I'm used to working with SRAM so if it only could be just as simple..

One (other) obstacle you'll face in using another DDR controller in Minimig
is that the controller needs to arbitrate between 68K and Z80 accesses - so
you'll notice there's two bus interfaces on the Minimig controller.

The Minimig does the arbitration within the controller itself, but I guess
there's no reason you couldn't do it outside the controller and leave it
unchanged - much like the arbiters in Altera's SOPC system. Some time ago I
wrote a simple arbiter for wishbone based on the example in the old wishbone
documentation...

Regards,

--
| Mark McDougall | "Electrical Engineers do it
| <http://members.iinet.net.au/~msmcdoug> | with less resistance!"