> there's no need to handle game pak interrupt at highest priority. only one
> interrupt is handled per entry to the main ISR (for most usual setups), so
> giving the lowest priority is fine.
I think I see what you mean. If you have multiple interrupts enabled like
how Nintendo has demonstrated, then a "lower priority" interrupt will
still preempt a higher priority one. The order that you check the IF
flags doesn't mean anything if any interrupt which happens preempts the
one you are currently processing.
It is like a store where any customer who comes to the counter will get
immediately served. It would be pretty annoying to a customer with a lot
of stuff to buy, but really convenient for those people with just a couple
of things. The problem is that if the person with just a couple of things
was being served, he would have to wait if the big customer came up behind
him him (but this is less likely because the small customer is so fast).
I guess interrupts that do not need to be preempted can set IME to 0. It
will be restored by the main ISR.
Hmm, how does the multiple interrupt process keep from processing the same
interrupt twice? If an interrupt high on the list was being processed,
and then an IRQ lower on the list occured, isn't there a situation where
the IF bit for the higher IRQ has not been cleared yet? In that case
wouldn't the ISR confuse which interrupt had occured?
I guess a true priority system would return from the ISR without clearing
the IF flag and handling the interrupt if the interrupt was lower
priority. I assume that if you return from your ISR without writing the
bits of the IRQs you handled to IF, that the IRQ will be immediately
reasserted.
In a single interrupt system, the order has meaning because the IRQs which
occur while you were processing the current IRQ will be waiting. When it
cames back into the ISR, the one highest on the list will get processed
first. I assume the IME simply keeps IRQs from being asserted, but that
if they are enabled in every other whay they still set IF and will be
asserted when IME is set to 1.
I dunno, the more I think about it, the more confused I get. Nintendo's
sample code seems to work just fine for the most part, so I must assume
that any questions I ask have satifactory answers.
I am concerned about how the multiple IRQ ISR knows if it is already
processing an interrupt in another context. Is the IE bit reset until
you reset the equivalent IF bit? If so, then that would explain the IF&IE
instruction and explain how it knows to only process new interrupts.
Is this explained in detail anywhere?
> but if you disable all interrupts, you'll never get the game pak interrupt
> if someone inserts the cart again. ;)
I guess if you are looking to allow reinsertion you should push the IE
onto the stack, clear it except bit 13, and then wait.
I was thinking in context of what a simple cart interrupt handler for
devkitadv might do. I would probably just reset IME and be done with in
that case. Anything more complicated would be up to the programmer to
override.
... there's no need to handle game pak interrupt at highest priority. only one interrupt is handled per entry to the main ISR (for most usual setups), so ...
... I think I see what you mean. If you have multiple interrupts enabled like how Nintendo has demonstrated, then a "lower priority" interrupt will still...
Jason Wilkins
fenix@...
May 2, 2003 2:50 pm
From: "Damian Yerrick" <d_yerrick@...> ... I've been wondering about that. The specs (e.g. gbatek) explicitly say that most of the cart ROM is locked...
Jonathan Perret
jonathan.perret@...
May 2, 2003 5:36 pm
... oops... I meant 'mb -1'. It's -1 to read a cart and -p to write. ... Perhaps Nintendo wrote that in the spec but didn't put it in the first generation...
From: "Jason Wilkins" <fenix@...> ... if you're handling a higher priority (in terms of its order in the branch table in the dispatch routine) interrupt,...
... Actually, it is. The IME is saved, and then set at the beginning of the ISR. Interrupts are still disabled in the CPSR, so interrupts are still disabled...
Jason Wilkins
fenix@...
May 4, 2003 12:31 pm
FYI People were talking about the cart removed interrupt. Well, be sure you disable DMA, or probably better yet, set the audio volume to zero in the loop while...
Mike Schwartz
mykes@...
May 4, 2003 5:02 pm
... more ... DMA ... a ... additional ... Yes, that's a good question IMHO. In a non-embedded OS it is generally considered very bad practice to have...
Jonathan Perret
jonathan.perret@...
May 5, 2003 1:00 pm
... Now, of course the issues are not the same on the GBA; if there's just one handler that occasionnally needs more time to do its work perhaps it's not...
... The multiple interrupt code in my crt0.S is nearly identical to Nintendo code as a result of my "review" :-) of N examples. However, I made small changes...
... interrupt handler Well, I guess, although it seems to be more of a 'timed request processor'. ... return immediately to the BIOS while user control returns...
... Part of the point I was trying to make is that switching the CPU back into System mode to execute the handler, then returning to IRQ mode just before...
Jonathan Perret
jonathan.perret@...
May 7, 2003 3:29 pm
Okay you guys have sucked me into this. My limited understanding of how ARM sees the world is the same or similar to where some of these ideas are headed. I...
Anyway, yes, umm, and, anyway, in theory, anyway, I didnt proof read that before I sent it...sorry. The encoding of the LDRT is not obvious, apparently there...
... This is exactly what I was thinking about, but you state it 100 percent more clearly than me....
Jason Wilkins
fenix@...
May 8, 2003 8:42 am
From: "David Welch" <gba@...> ... Very much agreed. ... The LDRT/STRT instructions look yummy. I have an "ARM7TDMI data sheet" (arm7tdmive.pdf) here and...